A conventional storage apparatus uses a magnetic disk, an optical disk, or other such random access-enabled nonvolatile storage medium as a data storage medium. Today's mainstream storage apparatus comprises multiple small-sized disk drives.
In line with advances in semiconductor technology in recent years, batch erasable nonvolatile semiconductor memory has been developed. One such nonvolatile semiconductor memory, for example, is a NAND-type flash memory. A storage apparatus, which uses flash memory as the storage medium, is considered to be superior to a storage apparatus comprising multiple small-sized disk drives in terms of power savings and faster access.
A flash memory will be explained here. In a flash memory, a block is a storage area, which is a unit for the batch erasing of data, and a page is a storage area, which is a unit for reading and writing data. As will be explained further below, multiple pages are disposed inside a single block. The characteristics of the flash memory make it impossible for stored data to be directly rewritten. That is, when rewriting stored data, the flash memory saves stored valid data to a different block. Next, the flash memory erases the stored data in block units. Then, the flash memory writes data to the erased block(s). Thus, the rewriting of data in a flash memory accompanies the erasing of data block by block. However, the time it takes to erase one block's worth of data in a flash memory is approximately one order of magnitude longer than the time required to write one page's worth of data. Therefore, the data rewrite performance of the flash memory declines when a block's worth of data is erased every time a page's worth of data is to be rewritten. In a ease where the storage medium is a flash memory, it is known that data is written to the flash memory using an algorithm, which conceals the time spent erasing data from the flash memory.
Normally, a flash memory data rewrite operation is performed using a system, which writes data one time to an unused area, and data is not erased each time data is to be rewritten. However, since the unused areas inside the flash memory diminish when data rewrites become repetitive, the need arises to restore the storage area to a reusable state by erasing unnecessary data, which has been written to the flash memory. Consequently, a block regeneration process, which copies only the valid data inside a block comprising old data to an unused area, and restores the copy-source block to a reusable state by erasing this block is known for the high-speed rewriting of data in a flash memory. This will be called reclamation hereinbelow. This reclamation is executed for a block in which there is a large amount of invalid data.
Meanwhile, the flash memory is limited as to the number of times data can be erased. For example, 100,000 erases per block are guaranteed. The problem is that, in a case where the number of erases of a certain block increases in accordance with data rewrites being concentrated in this block, it becomes impossible to erase data from this block, making this block unusable. For this reason, in a case where the storage medium is a flash memory, a process for equalizing the number of erases for each block is known for preventing data erase processing from being concentrated on a specific block.
Furthermore, in a flash memory, the read error rate increases over time even for a write-once page. An error, which occurs even when data is simply being stored like this, is called a retention error. To avoid this, an operation for writing a page for which a fixed period of time has passed since a write to another page is known. This operation is called a refresh. The problem of equalization already mentioned and the impact on performance must also be taken into consideration for a refresh.
In order to conceal data erase time and equalize the number of data erases, which were mentioned above, a flash memory module performs a logical-physical address translation process for translating a logical address to a physical address at the time of a data write. The flash memory module comprises one or more flash memory chips, and a flash memory controller for controlling the reading/writing of data from/to the flash memory chip. This flash memory controller performs the logical-physical address translation process. The flash memory controller also stores information for the logical-physical address translation process as a logical-physical address translation table. Hereinbelow, the logical-physical address translation process may be called logical-physical translation, and the logical-physical address translation table may be called the logical-physical translation table.
The logical-physical translation plays an important role in the efficient use of the flash memory. In a case where a logical-physical translation with a low degree of freedom is used, the size of the logical-physical translation table is held in check, but performance declines as a result of frequent reclamations. Alternatively, in a case were logical-physical translation with a high degree of freedom is used, the size of the logical-physical translation table becomes enormous, and, in addition, the cost of control greatly increases. In order of solve for these problems, a method for using a specific area inside a block as an update data storage area, and a method for retaining multiple FTLs (flash translation layers), which are control layers for a flash memory comprising a logical-physical translation table, and switching to an optimal FTL in accordance with a type of access are known (for example, Patent Citations 1 and 2).    PTL 1: Japanese Patent Application Laid-open No. 2009-64251    PTL 2: Japanese Patent Application Laid-open No. 2006-221627